1. Field of the Invention
The present invention relates to integration of high-voltage and low-voltage MOS transistors, and more particularly, to a method for producing high-voltage and low-voltage salicide process.
2. Description of the Prior Art
As the scale of integrated circuits (ICs) has been rapidly decreased, the design and layout rule becomes more stringent. Moreover, as the integrated circuits (ICs) are fabricated to be more compact, the integration of ICs with different application becomes indispensable.
In the conventions, the integration of the high-voltage and low-voltage MOS transistors are majoring used to polycide process without salicide process. The great of reasons are
for the sake to strengthen the ability of junction breakdown in high-voltage MOS transistor, the N.sup.+ -type region to polysilicon layer of gate has N-type grade area, while implanting the energy with N-type ions into the grade is usually considerably height (&gt;100 KeV). Therefore, according to the old tradition of the salicide process of polysilicon layer with the gate, the high energy of implanting N-type grade is embedded in the channel under polysilicon layer of result in the shift of threshold voltage of high-voltage MOS transistor. PA1 the silicidation region is not formed above the top surface of N-type grade region. If the silicidation region is formed, the current will flow along the upper surface with silicidation region to reduce the ability of junction breakdown.
FIGS. 1A and 1B shows the cross section of a conventional high-voltage and low-voltage MOS transistors, which usually includes a silicon substrate 100, field oxide regions 120, an N.sup.+ -type source/drain region 160 of high-voltage and low-voltage MOS transistors, a polysilicon layer 140, and a WSi layer 200. Then, the N-type grade region is only formed in the substrate of high-voltage MOS transistor. In the structure of the shown transistor, the silicidation region of the structure is not formed above the top surface of N-type grade region. If the silicidation region is formed, the current will flow along the upper surface with silicidation region to reduce the ability of junction breakdown.
For the foregoing reasons, there is a need for disclosing a structure and a method of fabricating high-voltage and low-voltage MOS transistors having self-aligned silicidation.